Referring to FIG. 1, a flow diagram of a conventional design optimization process 20 is shown. Conventional software tools 22 create a layout of a circuit using a design netlist 24, timing constraints 26 and several cell libraries 28 (i.e., 28a-28c). The tools 22 can optimize an area and a performance (speed) of the circuitry, but power optimization is neglected. Commonly, each cell in the cell libraries 28 is part of a family with different sized transistors for the same functionality. The cell variations give the design tools 22 a rich, wide variety of cells for area optimization and speed optimization. The different cells within a family have different power characteristics. However, a power adjustment 30 is conventionally performed as a post-optimization step. Furthermore, the tools often have no way to distinguish between static (leakage) power and dynamic (switching) power.
Static power consumption is caused by current leaking while the circuit is not switching. The leakage is often across terminals of the transistors that should be biased “off”. However, deep-submicron processes have small spacings between elements that cannot fully stop the current leakage. Static current consumption can be reduced by changing the process slightly to shift a threshold voltage (Vt) in the transistors. Higher Vt transistors leak less current (possibly by an order of magnitude or more) than lower Vt transistors. Static current consumption is also reduced by increasing gate channel lengths. Increasing the length between a source and a drain of a transistor causes a dramatic reduction in leakage currents. Another conventional approach is to make a width the transistor smaller. Channel width reduction results in a 1:1 leakage reduction. Cutting the channel width in half cuts the leakage current in half. All of the above leakage reduction techniques make the transistors slower. Only the channel width reduction technique reduces dynamic power.
Dynamic power utilization is caused mainly by switching activity. An equation characterizing dynamic power is provided in equation 1 as follows:P=CV2F  Eq.(1)where P is the power, C is a capacitance, V is the voltage swing and F is the effective switching frequency. Because dynamic power is directly proportional to capacitance and making transistors smaller results in less capacitance, making the transistors smaller is a primary mechanism for reducing dynamic power.
Static power dominated circuits commonly have low operating frequencies, low data toggling rates (activity), long periods of inactivity in the system (system duty cycle) and some circuits can gate the clocks to stop toggling during system inactivity. Dynamic power dominated circuits commonly have very high operating frequencies, high activity rates, high system duty cycles and often do not gate the clocks because of a high system duty cycle. A large amount of gray area exists between the two extremes, so circuit designers are usually not aware of which power mode is more important for the application.
A current power optimization methodology is to use synthesis tools (either pre-layout or post-layout) to reduce power based on information in the cell libraries. The synthesis tools first optimize for meeting the targeted timing (speed) criteria with a minimum cell area. The tools then try to replace existing cells with equivalent cells that consume less power (as defined in the cell library, usually defined as only static power or the static power averaged at some toggling frequency with a dynamic power). The synthesis tools cannot often replace all cells and still meet timing goals because the cells that consume less power are usually slower.
No distinction commonly exists between static power consumption and dynamic power consumption in the existing approaches. The cell libraries have power numbers that are valid only for a given operating frequency and activity rate that likely misrepresent the power for an intended usage. The existing solutions do not provide a method for optimizing power. The existing solutions only reduce the power consumption a little for a certain operating frequency. Furthermore, the single frequency used in the characterization is often inappropriate for large system-on-a-chip designs having several subsystems with different usages and different frequencies.
Conventional cell libraries used in the optimization also lack “monotonicity” in a speed/area ratio and a power/area ratio. For example, monotonicity in the power/area ratio means that for a given cell function, if the cell area increases then the speed and power of the cell increase as well. Because static power and dynamic power are two different variables with different causes, conventional libraries tend be non-monotonic. As such, reduction in area does not always mean a reduction in static power.